资源列表
MVB_test
- 此功能是实现曼彻斯特编码的Verilog代码,经过在xilinx sp6上实际运行证实可行。-This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.
crc7
- 以crc7为例进行UVM的验证 Part 1: 搭建环境。 本文使用的Quartus II 13.1(64 bit),器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是,没找到Modelsim自带的uvm_dpi.dll,于是,还重新编译了一番。 本文在win 10下。下载uvm-1.1d(现在最新版本有1.2d了),放好。(crc7 code by system verilog language)
AD
- 用FPGAZUO的一个32路AD程序,用VERLlog写 的-With FPGAZUO a 32 AD procedures, written with VERLlog
DE2_TV
- it s so easy and important
I2C_Test
- I2C接口模块,用于连接符合I2C总线接口标准协议的传感器或者其他设备。FPGA验证通过-I2C bus interface
FPGAandCPLDentry-leveldetailedstudymaterials
- fpga和cpld入门级详细的学习资料,内容很详细很全面。非常实用。-entry-level fpga and cpld detailed study information, the content is more comprehensive. Very useful.
THDB_D5M_CD
- Terasic TRDB-D5M CD V1.2.0
ICTCLAS50_Windows_32_C
- python中文分词\ CDict.py-Chinese word python \ python Chinese word \ CDict.py
DFCPU
- 用FPGA做的一个32路AD程序(用VERLlog写的)-FPGA to do with a 32 AD program (written by VERLlog)
src
- v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
DES_ALGORITHM
- Data Encryption Standard
Core8051
- VERILOG编写的Core8051实验例程,包括整个工程,周立功公司提供-VERILOG Core8051 written test routines, including the entire project, provided ZLG