资源列表
FPGA_OS
- 一个FPGA芯片上搭建系统的实例，包含了内核的建立，及在内核上运行的简单程序。-FPGA chip to build a system example, contains a kernel build, and run in the kernel of simple procedures.
B3LabGuide
- xilinx 的FPGA开发板的相关资料，可以很好地熟悉掌握开发板的使用，加快开发进度-Xilinx FPGA development board information, is a good way to master the use of the development board, speed up the development pro
CPU
- 不同方法实现的CPU系统。同样支持加减乘，逻辑/算术移位，与或非等建议指令。-Different methods to achieve CPU system. Also supports, subtraction, multiplication, logic/arithmetic shift, and the like or recommend instruction.
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
C-Embedded-Processor
- Costumizable Embedded Processor, design processor in hdl for asic or fpga
guibing
- 该设计采用VHDL语言将五个数的从大到小排序，采用的方法是归并插入排序算法。该算法能在最少比较次数（七次）情况下排列出五个数的大小顺序。-This design using VHDL language will be ordered five digits from big to small, the method is to merge insertion sort algorithm. The proposed algorithm can at least compare (seven) i
freq_counter
- vhdl编写的数字频率计,可用三个频段选择，Quartus II 8.1上测试通过-the frequence counter by VHDL，compiled by Quartus II
DDS
- DDS信号生成模块，使用MATLAB产生查找表，可输出方波、三角波、锯齿波、正弦波-DDS signal generator module, using MATLAB to generate a lookup table can output square wave, triangle wave, sawtooth, sine
SF-CY3-FPGA
- SF-CY3 FPGA套件开发指南Ver3.00,要学习的同学值得看一看-SF-CY3 FPGA Suite Developer' s Guide Ver3.00, students to learn is worth a look
frequency_counter
- 基于等精度方法的的频率测量的verilog代码，结合单片机使用-Based methods such as precision frequency measurement of the verilog code, combined MCU
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
fir
- 使用VHAL语言编写的一个fir滤波器，通过modelsim进行仿真-fir filter