资源列表
pinlvji
- 能实现等精度的频率计，测量频率大于1Hz以上的信号，可以测周期，频率，脉宽，占空比。-Equal precision frequency meter measuring frequency is greater than 1Hz or more signal can be measured cycles, frequency, pulse width, duty cycle.
ESS_GZ_V4.6
- 测试工装 电磁环境模拟器测试工装能够产生脉冲宽度、重复频率、输出信号功率可设置的射频脉冲信号及收发组件的各种输出信号，用于模拟器整机和信号采集处理单元的功能和性能测试。-Test fixtures Electromagnetic environment simulator test fixtures can produce pulse width and repeat frequency, the output signal power can be set rf pulse signa
4.6receive_and_send
- 控制CC2420的vhdl 保证很有启发意义-cc2420
antenna_position
- 本程序为船舶导航雷达天线方位部分的verilog程序，包含QPF工程。-This procedure for the marine navigation radar antenna part of the Verilog program, including QPF works.
FPGAReference-to-study
- FPGA参考学习资料， EDA技术的应用与开发-FPGA reference learning materials, EDA technology application and development
61EDA_H582
- 该文件主要是关于采用ERIOLOG设计可编程逻辑器件的文档-This paper is about verilog HDL.
Xilinx_FPGAexample
- Spartan-3E Starter Kit Board User Guide-Spartan-3E Starter Kit Board User Guide
eda
- 花了很长时间搜集来的基于cpld和VHDL语言的嵌入式程序-Took a long time to collect cpld and VHDL-based language embedded program
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac
plj.FPGA
- 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号，被测方波为信号发生器产生的方波信号，显示电路由TTL芯片及七段数码管组成的电路，自校正输出由CPLD输出已知频率的测试方波信号，可将其输入至测试端口，进行系统精度校正。 -The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test
11
- VHDL出租车计费器设计，课程设计完美通过优秀,各个功能模块讲解十分清楚-Taxi meter VHDL design, curriculum design the perfect through outstanding