资源列表
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法,(Verilog HDL)设计所需的模块有: (1)带PLL的全局时钟管理模块 system_ctrl_pll.v (2)OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig (3)OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 (4)SDRAM数据交互控制器Sdram_Control_2Port (5)VGA时序
MC8051_IPcore
- 51IP核_VHDL和Verilog编写,并通过编写的C语言源程序进行测试通过-The 51IP the nuclear _VHDL and Verilog, and written in C language source code for testing by
verilog-ppt-in-buaa
- 2013年北京航空航天大学verilog最新课件-2013 BUAA verilog TEACHING PPT
Verilog
- 一些用verilog编写的小程序,有全加器,计数器,比较器VGA显示,键盘扫描等-Some small programs written using verilog have full adder, counter, comparator VGA display, keyboard scanning, etc.
USB_ulper
- USB ulper Link Layer design, role of Host and Device
FPGAPVC_3
- 基于SDRAM的PCI采集,上位机为VC编写,桥芯片为PLX9054,项目已经做完,上传5个例程,已经验证通过-SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by
TrafficLight
- 通过硬件描述语言VHDL编程,实现交通灯功能,要求如下: ① 车辆传感器(C),检测车辆通行情况,用于主干道的优先权控制; ② 主干道公路路口安装有人员通过请求按钮(PQ),一旦有请求信息,控制器应按放行处理,否则按默认方式处理; ③ Online控制信号由交通控制中心发出,(Online=1)一旦它有效,则主干道放行,十字交叉路口控制器“失效”,Online=0十字交叉路口控制器恢复控制权; ④ 当次干道公路无车时,始终保持次干道公路红灯亮,主干道绿灯亮; ⑤ 当次
EP3C16_Nios_LCD12864
- 基于ep3c16-nios的12864液晶的驱动程序,简单明了,适合新手学习。-Based on ep3c16-nios 12864 LCD driver, simple and clear, suitable for novice to learn.
a
- 数字信号处理的FPGA实现中文版文档,这本书很经典值得学习-FPGA implementation of digital signal processing Chinese version of the document, this book is a classic worth learning
Digital-signal-processing-FPGA
- 本书详细讨论了FPGA在数字信号处理中的应用问题-This book comprehensively elaborated FPGA in digital signal processing application problems.
fasong_and_jieshou
- FPGA实现发送接收全过程,包括QPSK调制、载波同步-FPGA to achieve the whole process of transmission and reception, including QPSK modulation, carrier synchronization
mp3
- 实现,MP3播放器的硬件设计,主要是用内核的搭建和使用VHDL语言完成驱动的编写。-it is a mp3 player,written with vhdl.