资源列表
aybook.cn_xinrdksfks0630
- 关于嵌入式系统设计的比较经典的教程，实用性强-Comparison of embedded system design on the classic tutorials, practical
Palnitkar_Verilog_1996
- Samir Palnitkar-Verilog Digital Design Synthesis-SunSoft Press (1996)
SEG7_Timer
- 七段数码管时钟显示的verilog程序，开发环境quartusII7.0-Seven-segment digital tube display clock verilog program development environment quartusII7.0
camera_test6
- 摄像头数据进行3*3表格的处理 然后进行中值滤波，8级流水线，速度快-Camera data for 3* 3 forms processing and then median filter, 8 lines, fast
SEG7_Timer
- 一个采用数码管显示的数字钟，能设置时间和显示模式的切换-A digital display digital clock, can set the time and a display mode switching
SEG7_Timer
- 里面主要写的是数字钟的代码，程序准确，请大家放心下载-Which is mainly to write is the code of the digital clock and accurate procedures, please rest assured download
FFTVLSI
- fft in fpga logic implementation
MIPS32SingleCycle
- VHDL Implementation of a 32bit Single Cycled MIPS.-VHDL Implementation of a 32bit Single Cycled MIPS.
DSP-on-FPGA.pdf
- 数字信号处理的FPGA实现,介绍了用FPGA实现数字信号处理的技术-FPGA implementation of digital signal processing, digital signal processing using FPGA technology
u8051
- 8051VHDL原代码，编译成功，可下载到FPGA运行-8051VHDL
pal_disp
- 实现模拟PAL格式数据，并打包成BT656到监视器显示，过程中完成了PAL打包BT656，乒乓操作、监视器配置控制等-PAL to BT656 package, monitor control
ZX_SOPC0
- 基于FPGA的DDS信号源设计 1.输出信号为正弦波、三角波及脉冲 2.信号幅度可调,范围：1V~5V 3.调幅步长：10mV 4.信号频率为低频：10HZ~1MHZ 5.频率调节步长10HZ~100HZ频段为1HZ,100HZ~1kHZ频段为10HZ,1KHZ~1MHZ频段为100HZ 6.频率调节方式通过键盘输入 7.运用LCD显示信号的类型、幅度、调频步长、调幅步长-DDS source FPGA-based design 1. The output sig