资源列表
Sram(v0.2.20090115)
- SRAM FPGA编程 CYLOON2系列均可使用-SRAM FPGA programming CYLOON2 series can be used
VHDL-program
- VHDL实验程序。需要的可以在此基础上修改。-Program VHDL experiment. Need can be modified on this basis.
DE2_CCD_CV
- altera DE2 实验板专用 CCD驱动
1
- VHDL书籍可以很好的为学生提供简单的基础学习指导-VHDL books can provide students with a good basis for a simple study guide
usb
- 中级篇05：USB设备接口驱动，适合新手，可以直接实例化，内有原理介绍等文件，有代码，强力推荐-Intermediate Part 05: USB device interface driver, suitable for novice, can be directly instantiated with a schematic presentation and other documents, has the code, strongly recommended
EDK13.1
- xilinx 2011全国电子设计大赛赞助商 EDK 应用设计讲述了其嵌入式的应用-xilinx 2011 National Electronic Design Competition Sponsored EDK embedded application design describes its application
FPGA
- 常用的FPGA开发板的资料，方便大家查阅。-PGA development board used to facilitate access to information.
Verilog-Digital-control
- Verilog HDL数字控制系统设计实-冼进-源代码-4469-Verilog HDL digital control system design implementation- Xian Jin- source code-4469
zhitouzi
- 原创。掷骰子游戏，VHDL，quartus，北京邮电大学数电实验，实现随机掷骰子游戏，在数码管显示点数，点阵显示输赢，有开机动画以及开机音乐，可实现多人游戏等-games, VHDL, quartus,experiments of BUPT, pure originality,random game, in the digital display dots, dot matrix display winning or losing, there are boot animation and bo
CHANNEL_ESTIMATION_PROJECT
- 基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来-Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it
test_ddr2_ip
- ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
iic
- 使用的是FPGA单片机 通过IIC总线，对24LC04进行读写实验。写入512btye的数据，前256个数字为0到255，后256个数据为1。然后，将512byte数据读出来并打印。最后，对比数据是否相同，如果有不同，说明读写过程有错误-By using a single-chip FPGA IIC bus read and write on 24LC04 experiments. Write 512btye data, the first 256 digits from 0 to 255, a