资源列表
MySopc
- 自己亲自设计的软核，可以打开详细的设计细节，仅作为参考，自己用的话要根据自己的情况进行设计。-Soft-core own personally designed, you can open the detailed design details, only as a reference, they used words to be designed according to their own situation.
VerilogHDLDigitalControlSystem
- 《Verilog HDL数字控制系统设计实例》-冼进-源代码, Verilog HDL Digital Control System Design - Xian Jin- source code
多周期cpu
- 多周期cpu,11条mips指令集，仅供参考
pcpu_handle_mem
- Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
Clock
- VHDL语言编写的数字时钟程序，包括硬件设计的芯片管脚分配和功能代码等。功能包括时间的设定和显示。-VHDL language digital clock procedures, including hardware design, the chip-pin assignment and functional code. Features include time setting and display.
eda_files
- 利用SPOC builder 建立系统进而在这个硬件基础之上进行NIOS系统编程实现一些简单的小程序。-it is very easy ,you can leran it very fast.
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
AD_DA_Chip_test_program
- AD DA芯片测试程序 (开发环境keilC51+Quartus7.2)-AD DA Chip test program (Developmentenvironment： keilC51+Quartus7.2)
FPGA_LED
- NIOS II上实现，包含led的的控制verilogHDL，原理图的设计等等，直接用nios II打开就可以使用-NIOS II achieve control of verilogHDL contain led, schematic design, etc., directly nios II can be used to open
d_clock
- 基于QUARTUSII，电子时钟，可用，VHDL以及原理图。-Based QUARTUSII, electronic clock, available, VHDL and schematic.
hf_mot
- 电机驱动及编码器同步采样，内部兼具多重滤波采样处理算法。(Motor drive and encoder synchronous sampling, the internal multi filter sampling and processing algorithm.)
Logic-analyzer
- 一个逻辑分析仪的开发源码，包括单片机FPGA的所有程序，以及硬件的原理图。-A logic analyzer source development, including single-chip FPGA All Programs, and hardware schematics