资源列表
Clock
- VHDL语言编写的数字时钟程序，包括硬件设计的芯片管脚分配和功能代码等。功能包括时间的设定和显示。-VHDL language digital clock procedures, including hardware design, the chip-pin assignment and functional code. Features include time setting and display.
eda_files
- 利用SPOC builder 建立系统进而在这个硬件基础之上进行NIOS系统编程实现一些简单的小程序。-it is very easy ,you can leran it very fast.
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
AD_DA_Chip_test_program
- AD DA芯片测试程序 (开发环境keilC51+Quartus7.2)-AD DA Chip test program (Developmentenvironment： keilC51+Quartus7.2)
FPGA_LED
- NIOS II上实现，包含led的的控制verilogHDL，原理图的设计等等，直接用nios II打开就可以使用-NIOS II achieve control of verilogHDL contain led, schematic design, etc., directly nios II can be used to open
d_clock
- 基于QUARTUSII，电子时钟，可用，VHDL以及原理图。-Based QUARTUSII, electronic clock, available, VHDL and schematic.
hf_mot
- 电机驱动及编码器同步采样，内部兼具多重滤波采样处理算法。(Motor drive and encoder synchronous sampling, the internal multi filter sampling and processing algorithm.)
Logic-analyzer
- 一个逻辑分析仪的开发源码，包括单片机FPGA的所有程序，以及硬件的原理图。-A logic analyzer source development, including single-chip FPGA All Programs, and hardware schematics
FPGA-for-greenhand
- 本资料适合fpga初学者入门使用，包括：fpga设计资料大全，fpga的交流电机控制，fpga的中文培训教程-This information is suitable for beginners FPGA portal, including: fpga Design Sourcebook, fpga of AC motor control, fpga training course in Chinese
150M
- quartus_nios 综合开发平台，可以多中断，重要的是它的cpu可以工作在150M，总线工作在100M×32bit；-quartus_nios comprehensive development platform that can interrupt more important is that it' s cpu can operate at 150M, bus work in 100M × 32bit
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
DMASU
- nios中DMA数据传输方式的实例化程序-nios in the DMA data transfer mode of instantiation process