资源列表
Paralleladder
- 并行加法器VHDL代码，可实现五位加法运算-VHDL code parallel adder
sin_generator
- Sin Generator. 16 points on period.
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
ps2_key
- 这是PS2键盘解码试验，在EPM240开发板上验证过的-This is a PS2 keyboard decoder test, the development board verified EPM240
halfadder
- vhdl code for half adder using libero software
TLC
- traffic light controller
dpram_anu
- true dpram with using shared variable
SRAM
- 2. FSM is frequently used to design SRAM controller. Given the bubble diagram of a SRAM controller and its state-and-output table as shown below
Test
- verilog语言编写的分频程序及其testbench测试文件。fpga开发入门的好例子。-verilog divide written test procedures and testbench files. fpga development of entry-a good example.
trafficlight
- 本人编写的简易交通灯程序，希望对大家有用，并欢迎批评指正-I prepared a simple traffic light program, I hope useful for everyone, and welcome criticism.
cla
- Carry Lookahead verilog source file