资源列表
Solution_19
- This solution would help to study controller design. Especially Buck converter.
VGAdisplay
- 本系统编写了VHDL代码实现对对VGA协议的控制，可以在显示屏上显示分辨率为640*480，刷新频率为60Hz的彩条及彩色图片-The system is written VHDL code for VGA protocol for control can be displayed on the display screen with a resolution of 640* 480, refresh rate of 60Hz and a color picture of color bar
FPGA_ziliao
- 初学FPGA很好的资料，包括数码管、跑马灯、蜂鸣器等完整的工程-FPGA good beginner information, including digital control, marquees, such as the complete works buzzer
FPGA-Train
- FPGA基础培训，包括： FPGA基本架构 Xilinx工具流程 实验1：Xilinx工具流程演示 实验2：架构向导和PACE 实验3：全局时序约束 实验4：合成技术 实验5：CORE Generator系统 实验6：利用ChipScope-PRO-Basic FPGA Architecture Xilinx Tool Flow Lab 1: Xilinx Tool Flow Demo Architecture Wizard and PACE L
saopin_saveV2
- 在FPGA中利用DDS的原理实现了扫频功能并使用高速的AD采集数据，同时完成了数字峰值检波，并配合高速DA实现数据的输出-Use DDS principle in the FPGA to achieve the sweep function and use of high-speed data acquisition AD, while the completion of the digital peak detection, and with high-speed data output DA
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
Verilog_HDL-examples
- 黑金动力社区关于各种verilog的例程-Of black money motivation Community routines on various verilog
cw
- 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的-signal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for alte
ASIC
- 西安交大asic课件，对于数字集成电路的学习有帮助，经典-Xi' an Jiaotong University asic courseware for learning to help digital integrated circuits, classic
USB_1.1IP核
- 这是USB的一个机遇FPGA的IP核设计。欢迎大家使用
Verilog-design-and-identify-book
- 找到这本书的完整版了。呵呵，贴出来和大家共享。这是本好书，我买了一本作为Verilog的参考书。这本书语法部分集中，便于查阅，此外讲了很多实用的设计思想。最重要的是本书薄，可以完整看完。强烈推荐。 （如果只是查阅，电子版就可以，如要完整学习，建议还是买纸质版的）-Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog
TFT_FullDisp_V2.0
- Verilog HDL 语言构建驱动TFT LCD显示屏的详细方案设计-Verilog HDL language construct drive TFT LCD displays detailed program design