资源列表
NIOS_VGA
- 某高人自己写的VGA程序，VERILOG格式，经测试，修改后可用。-An expert to write the VGA program, VERILOG format, tested, modified available.
SoCKit_NET
- This Terasic HSMC-NET daughter sample program made by me, it demo how to use this daughter card.-This is Terasic HSMC-NET daughter sample program made by me, it demo how to use this daughter card.
signal_generator
- 信号发生器的FPGA实现，能输出正弦信号，方波信号，三角波信号-FPGA implementation of the signal generator can output a sinusoidal signal, square wave signal and triangular wave signals
internet_test
- xilinx SP605 板卡，网口设计。echo设计，实现接收单字符并返回的功能，同时从串口显示输出内容-Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time
GUI_for_AN431
- altera FPGA的官方驱动，可以给大家带了很多方便-offical driver for altera fpga
devided
- 一个16位除8位的除法器，能够输出余数和商。(In addition to a 16 bit 8 bit divider, can output the remainder and quotient.by stan)
source
- VHDL Altera example code
vivado_2014-4_2015-2_64bit
- vivado 2014.4-2015.2 64bit的全部license-vivado 2014.4-2015.2 64bit license
calendar
- 这是用Verilog写的万年历，里面包含的日月年各个模块。各个模块用Verilog写的，最后用原理图把各个模块组装成最终的系统。每个模块经过仿真没有问题，整个工程在板子上经过试验，能够完成万年历的功能。-This is the calendar write with Verilog, contains the sun and the moon years each module. Each module in Verilog written, finally the principle diag
CPUdesign
- 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。-Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
EDKlab
- 这是我这次参加的设计大赛时用的fpga的例程，可能对大家有用-This is my participation in the design competition this time with the fpga' s routine, may be useful for all
FIR
- 基于matlab的自己编的fir滤波器，简单易懂的亲~适合新手-Own series based on the matlab fir filter, easy to understand for novice pro ~