资源列表
JmsQuartzTest
- JmsQuartzTest JmsQuartzTest -JmsQuartzTest JmsQuartzTest JmsQuartzTest
SDRAM
- SDRAM编程代码，FPGA 的设计代码。(SDRAM programming code, FPGA design code.)
ex3-6-bank_no_sys
- 银行叫号系统，已经仿真验证，并且在硬件平台测试-Banks have simulation, snarling system, validation, and test the hardware platform
DigitalDesignofSignalProcessing
- This chapter begins from the assertion that the advent of VLSI (very large scale integration) has enabled solutions to intractable engineering problems.
hsk4571_sgna_generator
- 信号发生器的VHDL实现，可调节波形及频率，方波、锯齿波、三角波等，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Signal Generator VHDL implementation, adjustable waveform and frequency, square wave, sawtooth, triangle, etc., in QUATTUS | | 9.0 under preparation, can be
Day-3-Training-Material
- OneSpin培训资料 OneSpin广泛用于芯片设计的断言验证。-OneSpin training material can help user understand how to do assertion verification in ASIC design.
rom-test
- 简单的FPGA中ROM使用仿真程序，使用的verilog语言-Simple FPGA ROM emulator, using the verilog language
led_3_test
- 本源码实现了基于FPGA的3寸OLED的驱动，并能在屏上实现条纹显示和棋盘格显示。所使用开发板是CYCLONE 3,上传源码是整个工程，里面有源程序文件-The source implementation of FPGA-based 3-inch OLED driver, and can be implemented on-screen display and stripes checkerboard display. Development board used is CYCLONE 3, u
VHDL
- verilog程序包 包括数码管显示 lcd 红外线接收和读取 -Verilog package includes digital display lcd infrared receiver and read
spimasterslaveceshi2
- 串口主机和从机进行正常通信的FPGA实现，编译已通过。-Master and slave serial communication on FPGA normal, compiled has passed.
CIC_filter
- 抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。 注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal M
Hua-wei-FPGA
- 华为FPGA设计全套，我导师做课题时候给我的。-Huawei complete FPGA design, when I do the subject mentor to me.