资源列表
verilog
- verilog hdl 写的一个串口程序，编译仿真都已经通过-the verilog hdl write a serial program, compile simulation have passed
ucgui_test_cyclone4
- ucgui+ucosii在nios ii上的移植，支持ps/2鼠标驱动。包含整个工程。-ucgui+ucosii porting on nios ii, support ps/2 mouse. whole project included.
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过 ， 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
ALINX9226_DB4CE15_restored
- 本代码是用verilog编写的FPGA控制高速AD9226的程序，亲测可用，供大家参考。-this is a program for FPGA to control AD9226, which is useful by verilog.
sopc_led_burnflash
- sopc_led_burnflash 在FPGA上实现LED的闪烁-sopc_led_burnflash in the FPGA to achieve the blinking LED
FPGA
- 数字信号处理的FPGA 实现,这个是PPT-it is the FPGA TO REALISE dsp
DE2_115_TV
- This an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115-This is an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115
NIOS_UART
- NIOS_LED现成fpgaNIOS系统源代码，运行环境quartus II -NIOS_LED ready fpgaNIOS system source code, operating environment quartus II
user_design
- spartan3a-ddr2 (16bits 333M)
CRC_16
- 采用算法为：X^16+X^12+X^5 仿真验证通过，非常好用，大家可以用一下试试看(The algorithm is: X^16+X^12+X^5 The simulation verification passed, very good, you can use it to try it.)
cordic_IP_EP1C
- verilog编写的调用cordicIP核实现sin信号的完整工程-call cordicIP sin signal to achieve complete nuclear engineering verilog prepared
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.