资源列表
PIPELINE
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
FPGA
- 基于fpga的电子密码锁的源程序代码 可实现基本的电子密码锁功能-Fpga-based electronic lock of the source code can achieve the basic function of the electronic code lock
FFTFPGAVHDLcode
- 基于VHDL的 FFT 模块的开发 fft VHDL CODE 初学者值得一看的-VHDL-based development of the FFT module fft VHDL CODE beginner to see the
fft_IPcore
- 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
FPGA
- 清华大学FPGA培训讲义，不错的基础和阶进的教程-Tsinghua University, FPGA training handouts，A good foundation and order into the tutorial
ethernet_verilog
- 1000M以太网UDP协议在FPGA的实现源码，测试通过-1000M Ethernet UDP protocol in the FPGA to achieve source, the test passed
FPGA
- 培训班的讲义，和大家分享一下，希望能够起到它应该起到的作用！-Training course handouts, and to share with you, I hope to be able to play the role it should play!
ADS1256
- ads1256驱动代码，用verilog编写,在quartus上运行成功(ADS1256 driver code, written in Verilog, runs successfully on quartus.)
DivideByNCounter
- This folder contains the DividebyNCounter using verilog HDL -This folder contains the DividebyNCounter using verilog HDL
frequence_430new
- 基于FPGA的数字频率计的设计，可测量波形的频率周期占空比等-Digital frequency meter design FPGA-based, measurable frequency waveform cycle duty cycle
lvboqi_demo
- 基于fpga的程控滤波器的设计，verilog写的代码-Fpga-based programmable filter design, verilog code written
FPGATimeQuestAnasiseREV7.0
- FPGA那些事儿 TimeQuest静态时序分析REV7.0，需要的人员可以下载参考-FPGA those things TimeQuest static timing analysis REV7.0, needed can download the reference