资源列表
NIOS_JTAG_UART
- FPGA开发板上的JTAG——UART完成的工程设计，包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
pci32tlite_oc_latest.tar
- pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC s in ALTERA CYCLONE II FPGA).-pci32 taget core ip, The core has been designed to p
VHDL
- 关于学习FPGA很有用的资料，本人受益很大，愿与大家分享-About learning FPGA useful information, I benefited greatly, and is willing to share with you
61EDA_C2111
- 数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。--Verilog language implementation of the digital do
vga
- xilinx se spartan 3e advanced vga interface small cubes 800x640-xilinx se spartan 3e advanced vga interface small cubes 800x640
pipelined
- mips processor pipelined
user_first_fpga_20170620
- 程序可实验开发板上LED循环点亮，且可通过按键控制流动速度，用到了PLL IP 和 计数器模块。(Program with LED flashing circuit uses PLL IP and counter. And extinction rate is controled by key.)
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
VHDL2
- alter 硬件平台上实现中值滤波，实时性好-alter hardware platform median filtering,
file
- PAL-VGA格式转换器的设计,内部包含实现的FPGA代码-PAL-VGA format converter design, the internal code contains the implementation of the FPGA
71477225Nios
- altera nios对研究NIOS的人员很有帮助-altera nios research NIOS staff very helpful
ug871_vivad_HLS_tutorial
- Xilinx Vivado HLS 高层次综合工具的软件使用说明-Vivado HLS Xilinx high level integrated tool for the use of software instructions