资源列表
miao
- 数字钟 电子信息工程专业 EDA课程设计 管脚已经分配-Digital clock Electronic and Information Engineering course design pin has been assigned EDA
ISimChipScopeIPCore
- 这是我都记得FPGA资料，里面有ISIM,ChipScope,RAMorROM IPCore使用的教程，对于学习是很好的参考。(I remember FPGA data, there is an ISIM the ChipScope RAMorROM IPCore to use the tutorial, is a good reference for learning.)
vhdl译码显示器设计
- vhdl译码显示器设计，用quartus2软件编写，可实现数码管的显示译码功能。(VHDL decipher display design, written in quartus2 software, can realize the display and decoding function of the digital tube.)
20131201q_IR_gxy
- 这是调试红外的verilog代码，红外遥控输入的信息可以直接显示在数码管上-This is the infrared verilog code debugging information infrared remote control input can be displayed directly on the digital
Verilog
- verilog 课件十分很助于学习 ，因此要好好学习，天天向上 -verilog is very important,so we must study hard !!!!!!!!!!!!
F0501
- 汽车VCU控制器测试工装的程序，STM32单片机扩展总线读写FPGA内部RAM，DDS方式产生PWM，PWM频率，脉宽测量功能(Automotive VCU controller test tooling procedures, STM32 microcontroller expansion bus read and write FPGA, the internal RAM, DDS way to generate PWM, PWM frequency, pulse width measurem
median_filter
- 这已是一个有关中值滤波器的程序，为个人原创，实时性很好。-This is a median filter on the program, be original, real-time well.
2006441156
- 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看.. -the large number of routines, VHDL, VHDL programming for the study of great help, can not do ..
VHDL-Multi-fuction-Clock
- 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-T
Computer-Organization-experiment
- 上海交大计算机组成实验源代码 in verilog-computer organization experimentation source code
DE0_Nano_User_Manual_v1.5
- The DE0-Nano board introduces a compact-sized FPGA development platform suited for to a wide range of portable design projects, such as robots and mobile projects.
WUSB_XILINX_FPGA
- WUSB Xilinx FPGA verilog source code