资源列表
zhengyu
- 基于FPGA技术的等精度频率计设计代码，已通过调试-Based on FPGA technology, such as precision frequency meter design code has been through the debugging
fir
- 利用Verilog语言编写的FPGA作为数字fir滤波器的程序，在编译器中调试通过，可以作为模块调用。-the model of fir digital cr which is written of verilog language.
asyn_counter
- async counter,, test bench included-async counter,, test bench included..
16latch
- 16位锁存器，此程序通过quartusII软件调试通过
8255int
- 8259芯片中断控制LED 扳动SP按钮 LED点亮或熄灭-8259 Interrupt Control LED flip-chip LED lit or extinguished SP button
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
filer_pipeline
- 基于流水线的滤波器的设计与实现，verilog代码，xilinx，ISE，-Based on the assembly line of the design and realization of the filter, verilog code, xilinx, ISE,
fsm
- fsmatically delete the directory of debug and release, so please do not put files o
1221
- 频率设计，主要用VHDL来实现，是一个完整的课程设计，具有很好的通用性-Frequency design, the main use VHDL to implement, is a complete curriculum design, with good versatility
reset_module
- Reset control module
syn_detc
- Verilog语言的同步帧检测模块，适用于pcm通信系统，本模块可检测的同步帧为100110-The synchronization frame detection module implemented use Verilog language,for pcm communication system, the module can detect synchronization frame for 10,011,011
ps2_FSM
- This program is used to describe the mouse function on the FPGA board and it is very useful for the beginner on the FPGA board.