资源列表
fifo_vhdl
- FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
add1
- 可实现输入的2个一位十进制数的加、减运算。要求：输入提供十个数字键，先转化为8421码，再运算，输入的数据和输出结果都要以七段显示译码器显示出来（仿真波形）。输入模块、运算模块、数据转换模块要求用不同的模块分别实现。-Can be one of the input of two decimal addition, subtraction operations. Requirements: Enter the ten numeric keys provided, the first transfo
detector_unos
- detertor de unos, deterta si vienen 4 unos eguidos , maquina de estados
Sequential-detection
- 序列检测器的vhdl设计（用状态机实现序列检测器的设计，了解一般状态机的设计与应用。）-Sequential detection
22
- 这个是洗衣机控制器的代码，是用vhdl编写的，只有两个程序，有需要的用户可以下载-This is the washing machine controller code is written in vhdl, only two procedures, there is a need for users to download
CU
- This a example for Control unit-This is a example for Control unit
VHDL_VGA
- VGA的VHDL编程示例代码，对学习VHDL编程帮助很大-VGA programming examples of VHDL code, VHDL programming of great help in learning
control
- The Pipeline SPIN model using VHDL
pid
- pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................
Serial-port-sending
- 基于FPGA的串口发送程序，用VHDL语言编写，采用状态机的方法，可用串口调试软件进行测试-FPGA-based serial port procedures, using VHDL language, using the state machine approach can be used to test serial debugging software
changewin
- 用verilog实现40比特的串并转换，激励文件同时写在程序中。-Use verilog implementation 40 bits of string and transform, incentive documents written in a program at the same time.
QPSK1
- 基于verilog的QPSK调制的程序，调试通过，有需要可以下载来参考-QPSK modulation-based verilog procedures, debugging through, there is a need to reference download