资源列表
shukongfenpinqi
- 数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
GrayCounter
- 计数器，能够由二进制计数器转化为格雷码计数器
RS422sent
- 基于RS422的数据发送器- RS422sent
FSMwithOutputsEncodedwithinStateBits
- FSM有限状态机FSM with Outputs Encoded within State Bits-FSM with Outputs Encoded within State Bits
pwm
- 带有死区的、频率可设置的PWM输出源码，实际中已经应用-With a dead zone, the frequency can be set in the PWM output source, have been applied in practice
loop
- loop filter IIR for pll Fm demodulator
SHIFT_REG
- SIMPLE SHIFT REGISTER.
mux2to1
- --按下学习板的KEY1键和KEY2键，LED灯会显示状态 --KEY3作为选择器的开关； --1高电平选通a路信号也就是key1，；0低电平选通b路信号也就是key2-- Press the learning board KEY1 key and the KEY2 key, LED lantern display the state- KEY3 as selector switch - 1 high level gating a channel signal is key1 0 lo
MASK_MODULATION_CODE
- MASK调制VHDL程序_好用_测试正确-The MASK VHDL program with _ _ modulation test
QPSK
- QPSK调制是数字调制解调中 最为常见的调制方式之一，此Verilog 文件可以在FPGA上实现QPSK的调制方式-QPSK modulation is one of the most common digital modem modulation scheme, this Verilog file QPSK modulation scheme can be implemented on FPGA
ps2pmu
- power management unit with ps2 interface