资源列表
4_10_vhdl
- 这是老师给但计数器程序，经过自己刚才调试过了，真的成功了，哈哈……，有需要就看看吧-This the teacher but to counter procedures, testing himself just over a really successful, ha ha ... there is a need to watch it!
sfifo
- verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
multiplier1
- vhdl for multiplier and booth multiplier encoder table
generate_fang
- CPLD产生方波函数，可以任意改变占空比，在EPM240上实验通过。-CPLD generate the square wave function, can be changed to duty, in the experiment by EPM240.
cdkz
- vhdl编写的彩灯控制程序，比较简单，仅供初学者参考-vhdl prepared by the Lantern control procedures are relatively simple, reference is for beginners
dds_vhdl
- dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
CODE_GEN
- 北斗、GPSC/A码生成器的verilog ，输出速率可调，使用verilog编写- FPGA-based GPS receiver complete code of the spreading code generator design using verilog language
ADC_Control
- FPGA的ADC CONTROL程序，已在DE2开发板实测，可用。-The FPGA ADC CONTROL program, has been in the DE2 development board test, available.
ps2
- ps2键盘扫描程序verilog实现，将按键值转化为扫描值-ps2 keyboard scanner verilog realization, the key will be converted to scan values
fir
- This a verilog code for FIR filter works good on linux and windows platform-This is a verilog code for FIR filter works good on linux and windows platform
qudoudong
- 多按键去抖动电路VHDL源码，按键个数参数化，每个按键处理调用了上面的模块：-Many buttons to dither circuit VHDL source, the number of key parameter, each key, the call to the treatment of the above modules:
uart_if
- ram source read mode UART CODES.