资源列表
FSKmodulation
- 利用硬件描述语言VHDL实现的数字信号FSK调制-A VHDL program to realize the FSK modulation of digital signals
DATA
- ８位输出端口模块，可用于配置在FPGA中，verilog语言编程实现-8-bit output port modules can be used to configure the FPGA in, verilog language programming
clocktest.vhdl
- 时钟测试，vhdl，四位状态灯的转换，有复位信号-Clock test, vhdl, four status lights conversion, there are reset signal
jtdVHDL
- 用VHDL语言完成了一个交通灯的设计 设计较简单 一看就明白-VHDL language used to complete the design of a traffic light design relatively simple to understand at a glance
vga
- 用VHDL 编写的vga程序 基本功能都能实现 横竖之类的。-Using VHDL vga-program the basic functions can be achieved if they had the like.
JTD
- 交通灯的控制-Control of traffic lights!!!
vhdl1
- mesure de la largeur d une impulsion en vhdl
Adder12_4-3
- This an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.-This is an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.
truncation
- truncation using vhdl
sequential-detector
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试-With a state machine sequence detector design, and its simulation and hardware testing
demapperSharp1(16QAM)
- This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
25mto8k
- fpga编码，vhdl，将25m信号分频为8k信号，已仿真验证-fpga 25m to 8k