资源列表
fifo_sync
- 脉冲同步电路,简单修改就可以使用,很使用的.
mm1
- 基于随机数组中的最大值与最小值的选择器，可自由设定输出时钟和数组大小-Maximum and Minimum Value Selector
TXD
- TxD - simple RS232 transmitter
myfir
- fir滤波器的源代码 基于乘法器结构的线性相位滤波器-The source code for fir filter structures based on linear phase filter multiplier
second
- 0-99秒表数码管显示，有停止，启动功能-0-99 stopwatch digital display, a stop-start function
testad
- 此模块是FPGA系统中的指示模块，可分别指示系统的正常工作，程序烧写，工作模式，等状态，控制5个LED的状态来达到指示系统工作的目的-This module is the instructions in the FPGA system module, can the normal work of the indicator system respectively, burn written procedures, work patterns, such as state, control the
FSKmodulation
- 利用硬件描述语言VHDL实现的数字信号FSK调制-A VHDL program to realize the FSK modulation of digital signals
DATA
- ８位输出端口模块，可用于配置在FPGA中，verilog语言编程实现-8-bit output port modules can be used to configure the FPGA in, verilog language programming
counter_decrement
- counter which counts from 15 to 0,15 to 1 ,15 to 2 similarly till 15 to 15
Proj
- verilog/vhdl 串行口232通信程序-Spartan3E开发板调试通过-verilog/vhdl serial port communication program-Spartan3E 232 development board debugging
vhdl1
- mesure de la largeur d une impulsion en vhdl
Adder12_4-3
- This an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.-This is an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.