资源列表
quanjiaqi
- 4 级流水方式的8 位全加器-Way flow of 4 full adder 8. . . . . .
ktf
- 这是一个用VHDL编写的占空比可调的程序，对一个刚刚入门的FPGA的学员来说可以起到一个引导作用，简单但能学到很多东西-This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot
uart_test
- Test For The Universal Asynchronos Received and Transmitter
MAJ_Function
- Para calcular la funcion MAJ del algoritmo SHA
Control
- 维特比译码器控制器部分Verilog代码-The controller part of the Viterbi decoder in Verilog code
clock_top
- 基于cx200a的fpga的数字时钟系统的设计，-Fpga based cx200a of the digital clock system design,
combinational_divider
- 参数可配置的除法器verilog源代码，验证通过-verilog soure code for divider with configurable parameters
vhdl
- VHDL实验 数字密码锁的设计与实现-Design and Implementation of VHDL experimental digital lock
zero_comparator
- zero comparator in VHDL
led
- 用VHDL编程点亮发光二极管，并实现二极管循环点亮的功能 -Light emitting diode, light diode loop using VHDL programming
lift
- 用Verilog语言和实验箱上的按键和灯，实现三层电梯简单的上下楼和开关门。-With buttons and lights Verilog language and experimental box, simple to implement Layer elevator downstairs and switch on the door.
data_select4
- 四 路 数 据 选 择 器，从 四 路 数 据 选 择 一 路。-Quad data selector, all the way the four data.