资源列表
HY57V64_control
- 本代码用verilog而不是直接在nios中用ip核来实现HY57V641620FTP-6的读写，时序完全正确，从串口输出来验证的数据完全正确。附带说明和参考资料。希望对您有帮助。-This code is used instead of directly in verilog ip core nios used to achieve HY57V641620FTP-6 reading and writing, the timing exactly right, from the serial d
demo_VGAcolpattern
- DE2-70 VGACONTROLLER FPGA
sopc
- 文件包括：FPGA及DSP+Builder Nios II Software User guide chinese NIOSII那些事 Nosi Ⅱ入门 SOPC系统设计入门教程-Documents include: FPGA and DSP+ Builder Nios II Software User guide chinese NIOSII those things Nosi Ⅱ entry SOPC Design Tutorial
l_standard_1c6
- RT8019网络控制器在FPGA中的驱动设计-RT8019 network controller in the FPGA design of the drive
mcu51
- 基于IP核的51mcuFPGA程序，有顶层文件图，可以直接运行，有助于对mcu的工作原理和FPGA的理解-IP core based on the 51mcuFPGA program, there are top-level file map, can be directly run, contribute to the working principle of the MCU and FPGA understanding
pinlvji
- 等精度频率计设计，很好的源代码，附上工程文件，在quartus5.0以上版本即可运行。-Design accuracy, such as frequency meter, a good source code, attached to the project document, in the above quartus5.0 to run.
nois_led
- 通过编译及可运行的Nios II测试程序-Compiled and can run through the Nios II test program
SR_DDS
- DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。-DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.
CLOCK
- 实现电子钟，连接数码管显示，手写原创，使用CYCLONE V ，已经验证成功，附上工程文件-Implement electronic clock, use CYCLONE V, has been successfully verified, attach the project file
inequal-lenghth-code
- 不等长编码的设计，对莫尔斯电码的改进，用vhdl实现-Unequal-length coding design, Morse code improvements, using vhdl
quartusii_v10.1_handbook
- QuartusII 10.1的使用手册，非常详细，解决各种问题-QuartusII 10.1 user manual is very detailed and solve problems
uart3
- 实现多个串口通信，这里是两个各，两个会了，多个也一样，版本qurtus11.0，nios：nios_11.0-you can have ues this rs232 conmunition, qurtus11.0，nios：nios_11.0