资源列表
WinFilter08
- WinFilter is a software tool provided as freeware to design digital filter.-WinFilter is a software tool provided as fr eeware to design digital filter.
DES-source-code-by-HDL
- HDL实现的DES算法，及相关的Test bench激励文件-HDL achieve the DES algorithm, and the related documents incentive Test bench
dpll0226
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
pll1218
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
zhenxianyuxian
- zhe me duo shuo ming a da jia kan zhe xia zai ba-zhe me a duo shuo ming da jia kan zhe i gonna ba
usingVHDLtoimplementUART
- 利用VHDL语言开发一个UART的源代码，极具帮助价值！-use of VHDL development of a UART of source code, to help highly value!
7064
- vhdl代码写的一个密码锁程序，用EPM7064SLC44-10就可以实现-vhdl code written in a code lock procedures used EPM7064SLC44-10 can be achieved
ADC_16bit
- 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware descr iption language of 16 Digital to Analog source code can be integrated
my_ip_core
- 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
DE2Project_restored
- 2006nios嵌入式系统电子设计大赛时用过的完整工程。-2006nios Embedded System Electronic Design Competition used when the integrity of the project.
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source