资源列表
DE2_WEB_QII_60
- ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
DE2_synthesizer
- ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N,官方历程(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
DE2_TV_New_v1
- ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
DE2_TV_New_v2
- DE2官方板子程序，ALTERA官方代码，cyclone ii EP2C35F672C6N代码(DE2 official board procedures)
variable_duty_cycle_pwm
- VHDL project in ISE Xilinx for PWM generation
rgb_to_ycbcr
- RGB转Ycbcr实验,基于av6045开发板例程。(RGB to ycbcr base av6045)
idkdt
- SNR largest independent component analysis algorithm, Calculated transmission characteristics and reflection characteristics of the one-dimensional photonic crystals, Including quaternion various calculations.
标准SDR SDRAM控制器参考设计，Lattice提供
- 说明： SDR SDRAM 控制器 来自lattice 已经分析代码可用!大家可以参考修改，形成自己的实例(Descr iption: SDR SDRAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples)
超声波电源程序基础
- msp430单片机计算频率控制字 然后将控制字传递给dds芯片合成高频电信号(The MSP430 microcontroller calculates the frequency control word, and then passes the control word to the DDS chip to synthesize the high frequency electrical signal)
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
yui_dy42
- Linear array using cut than learning laid upon the right control of the main sidelobe ratio, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. Using high-order cumulants of MPSK signal modulation recognition.
jeday
- This is the second energy entropy matlab code, Signal Processing ESPRIT method, GSM is GMSK modulation signal generation.