资源列表
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
UART
- UART串口通信模块：包括接收模块RXD、发送模块TXD、分频模块FREDIV(UART serial communication module: including receiving module RXD, sending module TXD, frequency division module FREDIV)
LAB2
- zynq上实现流水灯的软硬件协同设计，利用vivado 2015.2版本eda软件开发。(Zynq realizes the design of hardware and software of water lamp, and uses vivado version 2015.2 EDA software to develop it.)
夏宇闻数字逻辑设计.pdf
- 顺序操作和并行操作，是新手们很容易混乱的一个重点。但是为了将低级建模发挥到极 限，这一点必须好好的理解.(Sequential and parallel operations are a key point of confusion for beginners. But in order to bring low-level modeling to the limit, this must be understood.)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
Z-turn-examples-master
- # Z-turn-examples The repository with my simple Z-turn examples, to be used as templates for more serious projects. Please note, that the Buildroot configuration in my designs sets the root password to "test". Setting the password is n
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
超声波测距模块
- 本人做的一个项目中的其中一个模块——FPGA超声波测距，很好用(Design of ultrasonic distance measuring module improved by using FPGA)
PLL
- xilinx pll 例程示范，完整的一个PLL例程，并有工程文件(xilinx pll routine ise project ,test file)
uart
- VHDL CODE FOR UART IN DEEP MODIFIED
timing
- Verilog实现计数器并送六位数码管实时显示(Verilog realize the counter and send six digital tube real-time display)
color_converter_latest.tar
- 彩色空间转换的VHDL源代码，可以实现CIE XYZ<->RGB， different RGB<->RGB和RGB<->YCbCr之间的相互转换，使用3x3矩阵模板(a color transform tasks such as CIE XYZ<->RGB, different RGB<->RGB and RGB<->YCbCr operations. The main part of color conversions f