资源列表
FMT
- 基于vhdl设计的数字频率计，后面还加了个与fpga通信的模块(Digital frequency meter based on VHDL design, and later added a module to communicate with FPGA)
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
i2c_latest.tar
- 基于verilog的I2C接口协议代码，支持EEPROM(Verilog based I2C interface protocol code, support EEPROM)
数字信号处理的FPGA实现-第三版-verilog源程序
- 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
nbwpm
- Data packet transfer source program, Chaos indicator for Lyapunov index calculation, Really is a good program.
DDS
- 基于FPGA的DDS正弦信号设计，文件中有源代码(Design of DDS based on FPGA)
diver
- 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)
m_manche
- 有关于M序列的曼彻斯特编码，亲自验证有效。(The Manchester code of the M sequence is personally validated.)
Y_0D
- 带同步置1、异步清0的D触发器。详细的讲解，易懂。(D flip-flop with synchronous 1 and asynchronous clear 0. Detailed explanation, easy to understand.)
T_0D
- 带同步清0、同步置1的D触发器模块。希望能够帮到大家。(D trigger module with synchronous clear 0 and synchronous setting 1. I hope I can help you.)
JBD
- 基本的D触发器，可实现基本的保持功能。输入到输出不变。(The basic D flip flops enable basic retention functions. Input to output remain unchanged.)
KEYPD
- Keypad sample. Vhdl language