资源列表
seven_seg
- a seven seg display module
ASCI_TRAFFIC_LIGHT
- 用VERLOG实现交通灯程序，有红绿两种灯，绿灯到红灯，路灯闪10秒，可以调整红绿灯持续时间-VERLOG achieve with traffic lights procedures, two black lights, the green light to red lights, flashing lights for 10 seconds, can be adjusted duration of traffic lights
cpldtoPCvhdlcoding
- CPLD与PC机通讯的VHDL代码，实用性强。-CPLD and VHDL code PC, communications,
SPI
- design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS
top
- 动态可重构的顶层设计，给出了所有的静态逻辑和端口设计啊-top design for PR
VGAHIGH
- 640*480分辨率直接写屏幕，使用BorlandC++3.1开发-640* 480 screen resolution direct write, use BorlandC++3.1 development
decoder3_8
- -译码器输出是低电平有效。所以每一次只有一个低电平。 --KEY1键和KEY2键和KEY3键作为 A b C信号的输入。LED灯作为输出显示状态 --按键的默认状态是1 高电平 --当按键按下时 对应的I/O为低电平（0）， --为了得到不通的值，三个按键不按下时，都是111.表示7；三个按键都按下时,都是000.表示0-- The output of the decoder is active low. So every time only a low level.- KEY1 a
ALU
- 8-bit unsigned, 16 operations(arithmetic and logic).
calculator
- simple VHDL calculator
SSD2
- 在Xilinx7.1平台下编写，可以实现七段数码管的译码功能！-Xilinx7.1 platform in the preparation can be achieved and seventh of the decoding functions of digital tube!
spi2-testbench
- test bench for spi communication
hello
- VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。-VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fas