资源列表
Verilog HDL 简明教程
- Verilog HDL是一种硬件描述语言，本书是Verilog HDL的入门教程
eetop.cn_ISCAS89(verilog)
- ISCAS89测试基准电路，verilog编写，可用于测试向量的生成(iscas89 benchmark, written in verilog language, can be used to generate test pattern)
GPU_LDPC+硕士毕设论文详解
- QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)
Xilinx High Speed Cable 驱动
- XILINX高速烧写器仿真器驱动程序软件下载文件(XILINX high-speed loader emulator driver software download file)
SRIO_DSP_X1
- xilinx 7 系列fpga与dsp srio数据传输(fpga and dsp communation with srio)
rdf0244-zc706-pcie-c-2015-4
- 利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
Xilinx_Vivado_Design_Suite_HLx_Editions_2018.2
- vivado 2018.2 license
lcd_test
- FPGA LCD 显示例程,在AN430的LCD模块上配备一个4.3英寸的天马 TFT-LCD模块(TM043NBH02),显示像 素为480 X 272,包含 LED 背光单元,采用真彩色24位的并行RGB接口和开发板连接(FPGA LCD display routines, equipped with a 4.3 inch AN430 module (TM043NBH02) on the LCD module of the TFT-LCD, displaying images.
Verilog俄罗斯方块
- 本设计是verilog设计的俄罗斯方块，含有所有的源代码。(This design is Verilog designed Tetris, which contains all the source code.)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
Altera+OpenCL
- Altera的OpenCL主要面向信号处理类应用的客户，是用C语言开发FPGA的利器，开放计算语言(OpenCL)联盟著名的公司有FPGA巨头Altera、两大显卡GPU巨头AMD、英伟达、CPU巨头Intel、软件和服务器巨头IBM以及全世界最大的公司Apple（苹果）等等。不过AMD和英伟达是用GPU实现的OpenCL并行运算，Altera是用FPGA实现并行运算。(Altera's OpenCL is mainly a client for signal processing applic
中级篇03：UART，波特率115200与PC通信
- 本程序实现FPGA的串口通信功能，可以进行数字字符等的发送，波特率为115200(This program implements the serial communication function of the FPGA, and can transmit digital characters, etc., and the baud rate is 115200.)