资源列表
5renduoshuVHDL
- 5人多数表决VHDL源代码，数码管可以显示倒计时时间和通过的人数-5 Most of the voting machine
VHDL1
- 4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出-4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
myCLK
- 24Mhz的频率分成2Mhz的频率。 再由一个I/O口输出。-The frequency of 24Mhz into2Mhz frequency，Again by an I/O port output.
parity_check
- Parity checing program in verilog
soma_loka
- Sum make in vhdl code
Freq_Divider
- frequency divider fpga get slow frequency
sn7448
- verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
fifo.v
- This the source code for FIFO -This is the source code for FIFO
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
Decade-Counter
- decade counter with two input and count out outputs