资源列表
baseball
- 用VHDL开发的棒球游戏,可以在QuartusII环境下编译,适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
K100_SONGER
- VHDL计数器
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
uart_core_vhdlORverilog
- 串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
8051core_vhdl
- 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
SPI_VHDL
- SPI串口的内核实现(vhdl),可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
VHDLverilogshirenqiangdaqi
- 用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器,乘法器,除法器,多路选择器,二进制转BCD码,加法器,减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
traffic_lamp
- 用verlog语言编的又一个很好的综合实验(交通灯的控制),特别适合于FPGA/CPLD的初学者-verlog language used is an addendum to the good of the experiment (traffic light control), particularly suitable for FPGA / CPLD beginners
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
fpga(CAN)
- fpga实现CAN总线控制器源码,每个项目都有说明文件,介绍使用方法。-fpga CAN Bus Controller source, each with explanatory documents on the use of methods.