资源列表
simple_fifo
- verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
dzzh
- eda课程设计:数字钟--vhdl语言全部源代码
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
234352325DECL7S
- Quartus环境下的7段译码管的扫描显示电路-Quartus environment of the seven decoding of the scan show circuit
123424475SINGT
- Quartus环境下的正选信号发生器的实验源码-Quartus environment is the election of signal generator FOSS
55478362cntshow
- Quartus环境下的12进制计数器的扫描显示电路-Quartus environment of the 12 counter-band scanning display circuit
23565785scan_led
- Quartus环境下的7段扫描显示电路的源程序-Quartus environment of the seven scanning display circuit of the source
11223344scan_led1000
- Quartus环境下的1000进制计数器的扫描显示电路-Quartus environment under the 1000 counter-band scanning display circuit
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
fpu
- 利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
sdh
- 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform