资源列表
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
DCFQ
- 经典触发器，对初学者会非常有用的，希望可以多交流下。-classic triggers for beginners will be very useful and hope more exchanges under.
spant
- 一个在spantan3上实现的24路分频VHDL程序，实现方法简单，并且在硬件电路上跑过，可以直接使用。可以进一步修改成PWM程序。-a spantan3 achieved in the 24-way frequency VHDL procedures, simple, and the hardware circuits once ran can be used directly. Can be further modified as PWM procedures.
clock_top2
- 数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
loadGIF
- 使用sdk读取GIF文件 需要相应的vgsdk库来运行项目-use sdk read GIF files need vgsdk corresponding to the operation of the project
lxh_xulijianceqi
- 这是1个序列检测器,可以重复检测序列,在通信方面用的较多-This is a sequence detector, can detect repeat sequence, in communications with the more
VHDL_100_example
- 全面的VHDL例子，全是实际工作中的经验所得，精华中的精华，直接拿来用，站在前人的肩上，看得更远！-comprehensive VHDL example, are the practical work experience, the essence of the essence for use directly. standing on the shoulders of our predecessors, see farther!
m68_k
- motorola m68k VHDL描述-motorola VHDL descr iption m68k
simple_fifo
- verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
dzzh
- eda课程设计:数字钟--vhdl语言全部源代码
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0