资源列表
1800.2-2017
- 最新版 IEEE UVM standard(The newest UVM IEEE standard(2017))
FIFO
- FIFO code in verilog
i2c_master_ip_for_nios
- i2c master ip for altera nios, add in qsys
Vivado 2016.4 SRIO License
- Vivado 2016.4 SRIO License,已经在Vivado 2016.4 测试通过，可以生产位流。其他版本没有测试，估计也是可以用的(Vivado 2016.4 SRIO License, which has been passed in the Vivado 2016.4 test, can produce a bit stream. The other versions are not tested, and the estimates are also available.)
xapp1052
- 赛灵思官方pcie例程，官网下载需要注册登录，这边给大家另一个选择(Xilinx PCIe official routines, the official website to download the required registration login, here give you another choice)
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
Verilog的边沿检测技术_设计源代码
- 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
sdram_ov7670_vga
- 利用FPGA采集图像，实现系统检测，很好的采集图像的源代码(Image acquisition using FPGA)
add.v
- 这是verilog的加法器。它可用于超大规模集成电路设计。(This is an adder by Verilog. It can be used for VLSI design.)
_spi_test1
- data transmitted from FPGA to devices using SPI bus
_uart_test2
- data transmitted from FPGA to PC using COM PORT version 2