资源列表
vc2015_x64_14.0.24215
- windows 7 安装VIVADO 需要(Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215)
FPGA8 shuma
- 用四位数管显示八位数字并且向左滚动播放。(Four digit tubes display eight digit numbers and roll playback)
LS164
- 用verilog原因实现LS164移位寄存器(Implementation of the LS164 shift register with Verilog)
count
- 用verilog语言编写一个计数器，改参数实现不同时间的计数器(Writing a counter in the Verilog language)
LS165
- LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
20180125_5M_01
- 基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码，可以使用(ajhsjdhjkshfjhfsjkjksa)
数字钟
- 数字钟(Digital clock)
1
- curcuit simulation in Hspice
55680576lift
- 电梯的智能控，是很好的毕业设计选择，十分有用(The intelligent control of the elevator is a good choice of graduation design)
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
26518282FPGA
- ep2c20f484n的应用，具有很大的作用(The application of ep2c20f484n has a great effect)