资源列表
dayashankar_nair_verilog_2.2.tar
- finite state machine
dayashankar_nair_verilog_2.1.tar
- finitie strate machine
subtraction floating point
- subtract two number floating point (32 bit)
x264
- hwaccel = get_hwaccel
piccolo_verilog
- 采用verilog设计的一个piccolo密码算法的硬件实现(Hardware implementation of a piccolo cryptographic algorithm designed by Verilog)
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
DDS -changed
- DDS技术实现波形产生代码，可以编译下载学习使用！(DDS generate diagram program)
traffic_light
- 使用Verilog编写交通灯控制代码，能够直接进行运行仿真。(Using Verilog to write traffic light control code, can run the simulation directly.)
新建文本文档 (3)
- 在Verilog中使用函数，用always块实现较复杂的组合逻辑电路，阻塞赋值与非阻塞赋值的区别(Using a function in Verilog, a complex combinational logic circuit is realized with a always block, and the difference between blocking assignment and non blocking assignment)
1
- 简单的组合逻辑设计，简单分频时序逻辑电路的设计，利用条件语句实现计数分频时序电路(Simple combinatorial logic design, design of simple frequency division sequential logic circuit and Realization of counting frequency division timing circuit by conditional statement)
shuzizhong
- （1）24小时计时显示（时分秒）； （2）具有时间设置功能（时，分） ； （3）具有整点提示功能； （4）实现闹钟功能（定时，闹响）；((1) 24 hour time display (time, minute, second); (2) have time setting function (time and minute); (3) it has the function of whole point. (4) realize the alarm clock function
dif
- FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates