资源列表
frequency divider and testbench
- a frequency divider and test bench with simulation results
Viscosity_1.7.7[sn]
- Viscosicty is a vpn app
imports
- 用FPGA实现UDP/IP协议，对于想用FPGA实现UDP/IP协议的可以看一看(Implementation of UDP/IP protocol with FPGA)
ethernet_interface_20160424_A
- 基于Xilinx Spartan-6开发板，实现以太网通信(Ethernet communication)
PLL
- verilog编写的锁相环程序。可以对照参考(Verilog prepared by the phase-locked loop program. Can control reference)
Verilog教程-夏宇闻
- verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)
bcd counter
- Binary counter design in verilog
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
他和它的故事 VerilogHDL之系列笔记
- 他和它的故事之一些对verilog实验的思考和笔记。(Some thoughts and notes on the Verilog experiment.)
北航MIPS多周期
- 多周期流水线处理器的verilog实现。(The Verilog implementation of a multi cycle pipelined processor.)
ALU32
- 采用booth算法，实现了32位的ALU。(The 32 bit ALU is realized by using the Booth algorithm.)
KEY
- 使用verilog编写的用按键控制LED灯，对于初学者是很好的锻炼(Using the key to control the LED lamp with Verilog is a good exercise for the beginner.)