资源列表
IC设计流程和设计方法
- IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not h
秒表
- 秒表,vga显示，可修改时间，可设置闹钟(The stopwatch, VGA display, can modify the time, can set the alarm clock)
DE2-115_book_all_sourcefiles
- 逻辑设计电路DE2-115实战宝典范例源代码(Logical design circuit DE2-115 real battle case source code)
crc7
- 以crc7为例进行UVM的验证 Part 1： 搭建环境。 本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。 本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by system verilog language)
just_clock
- Just a clock made for basys3 in vivado.
Assignment_2_ver.3
- Small ALU with adder and multiplier, reworked
nexys4vgamouseoverlay
- Demo code for mouse, nexys4 made by digilent
Basys-3-Keyboard-2016.4-1
- Demo for keyboard, basys3 made by digilent
Basys-3-GPIO-2016.4-1
- Test for GPIO for basys3, made by digilent
i2s_interface_latest.tar
- i2s 接口的vhdl实现，可用于FPGA(i2s interface with VHDL)
Specman-master
- Some interesting file that contain I have no idea.
systemc-2.3.2
- Something interesting SystemC