MODELSIM 环境下的Verilog 源代码，实现全加器功能-MODELSIM environment Verilog source code, the entire increase functionality

基于DSP Builder的fir滤波器，及在Modelsim上仿真工程文件，是在做基于FPGA的fir滤波器的一部分-The DSP Builder-based fir filter, and on the simulation project file in Modelsim is doing FPGA-based fir filter part of the

在EDA实验课上面，自己编写的NCO程序，可以产生出比较真实的正弦波、三角波以及锯齿波，用VHDL程序编写，有modelsim仿真textbench程序-On EDA experiment, oneself write the NCO program, can produce more real sine wave, triangular wave and sawtooth wave with VHDL programming, have the modelsim simulation text