搜索资源列表
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
async_transmitter
- 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
async_receiver
- 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
vtopgen
- 【原创】生成各个子模块verilog文件的顶层文件，自动完成模块的互连。减少冗余的繁琐的劳动。提高工作效率。-[original] generation sub-module of the top verilog paper documents, automatically complete module interconnection. Reduce the tedious redundancy of labor. Raise working efficiency.
VB219
- （2，1，9）VB译码器Verilog代码
32bit.zip
- multiplier and divider verilog codes,multiplier and divider verilog codes
i2c_top
- This a code for Verilog for I2C-This is a code for Verilog for I2C
verilog
- verilog设计经验点滴 因为Verilog是一种硬件描述语言，所以在写Verilog语言时，首先要有所要写的module在硬件上如何实现的概念，而不是去想编译器如何去解释这个module-verilog technolog
synchronisation
- This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.-This circuit is a nice edge detector that gives yo
smic13g_hs
- 中芯国际130nm的库代码，希望能给各位工作带来方便和支持-verilog lib
xilinx_primitives
- verilog code for alu
nnARM_tb01_09_02
- arm processor verilog code
nnARM_tb01_07_19
- verilog code for ope processor
tfft
- 利用python产生verilog test 文件-use python to generate verilog test file
MIP-C
- mips-c指令系统,用Verilog实现-mips-c command systems, using Verilog realization of
IF_SIG_CONTROL
- signal controls using IF for verilog. it modified Xilinx. it use just red, yellow and green signals.signal controls using IF for verilog. it modified Xilinx. it use just red, yellow and green signals.
shiyan6
- 使用Verilog实现十分进和六进制，并组合成六十进制-Verilog is used to achieve progress and six band, and combined into six decimal
pds_zadaci
- compile stuff for verilog hdl
VCDdecoder
- 基于GTK-wave做的verilog test bench语法解析器 解析vcd file. 俺自己写的-VCD (Value Change Dump) file is widely used in industry. A VCD file is an ASCII file, which contains header information, variable definitions and the value changes for specified variables, or