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adder
- 这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descr iptions.
clk_generator
- 基于Verilog HDL的任意分频代码，由本人原创，可实现0.000001Hz的步进，跟网络上的大部分简单地分频不一样！-Devicetor descr ipted by Verilog，can reach 0.0000001Hz！
da
- 用Verilog 语言编写的DA转换程序，非常实用
filter
- 数字滤波器的verilog语言程序，为双精度的滤波器，可以实现10k低通滤波-verilog filter
TTLV-Nguyen-Vu-Quang
- THIS document was written by verilog code. It s content talkes about descr iption 64 FFT
suzipaobiao
- 这是用verilog编写的数字跑表 ，里面包含有程序和仿真图 通过编译-It is written in verilog digital stopwatch, which contains a program to compile and simulation map
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
my_booth_mp
- booth algotihm verilog design and test
scaler
- scaler verilog code include with test bench file
uart-master
- verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)