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dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
RS(255-233)decode
- 基于verilog HDL RS(255,223)的编译器源代码-Based on verilog HDL RS (255,223) of the compiler source code
FM0_encode
- 详细介绍了FM0编码，采用verilog编码语言-FM0 encoding, using verilog
ldcp_verilog
- ldpc verilog 程序 做ldpc硬件实现的可以-ldpc verilog procedures do LDPC hardware implementation can
Miller_encode
- 详细介绍了副载波Miller码的编码，采用verilog的编码方式。-Miller introduced the sub-carrier code encoding, the encoding using verilog.
VHDLFIFO
- 用Verilog 写一个8x16 的FIFO，完成先入先出的功能，并且在FIFO读空时输出EMPTY 有效信号，读指针RP 不再移动；FIFO 写满时输出FULL 有效信号，并且即使WR 有效也 不再向存储单元中写入数据(写指针WP 不再移动)。 -NO
reg_32bit
- quartus 2中使用verilog编写32位寄存器-32-bit register
lab3
- only for verilog , this is single cycle code for verilog
mux2to1
- code for multiplexer in verilog
uart1
- this is uart based verilog code for all the beginners
led3
- lcd interface in spartan3e code with verilog domine
BCH
- BCH解码与编码的verilog语言实现-BCH decoding and encoding verilog language
control
- 用Verilog HDL 语言描述的自动转换量程频率计控制器-Automatic conversion range frequency meter controller described using Verilog HDL
cla32
- verilog code for cla 32 bit adder
aes_crypto_core_latest.tar
- AES verilog source code working well very easy to understand!! Enjoy!
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
Doxverilog2.6
- 用于Doxygen的Verilog的语法解析器-Doxverilog is a nativ verilog parser (Verilog 2001) for Doxygen.
dIGITAL-CLOCK
- Verilog code for digital clock
arch_radix4
- Its verilog code for radix -4 cordic-Its verilog code for radix -4 cordic
verilog
- verilog code and test bench