搜索资源列表
oaVerilog
- openaccess与verilog互相转化时所用的源代码，在安装了openaccess的windows和linux上都可以使用。-openaccess with Verilog into each other when used in the source code, the installation of the windows and openaccess on Linux can use.
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
crc
- 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写
fre_division
- 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频
i2c.tar
- Verilog语言的I2C总线，完整的模拟。适合做FPGA开发。
ALU
- 用VERILOG实现ALU，实现各种算术运算，逻辑运算，移位运算等
Verilog_HDL
- Verilog HDL入门,学习的最好参考资料，可以极短的时间内学会
counter
- 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真
XHDL4[1].0.40
- 实现VHDL和verilog之间的语言转换，方便程序之间的以致，XHDL版本4.0.40。-Achieved between VHDL and verilog language conversion between programs so easy, XHDL version 4.0.40.
key_interface
- verilog写的程序，是带按键消抖程序。。对于新手具有参考-verilog write the program, with key debounce program. . A reference for the novice
key_scan1
- 用verilog语言描述的键盘扫描程序，用于FPGA芯片以及矩阵键盘的测试。-With verilog language keypad scanning procedure.For the FPGA chip and matrix of the keyboard.
lsb
- 用verilog语言写的拔河游戏机，配套硬件试验箱-Verilog language used to write the tug-of-war games, matching hardware chamber
Final_Project2
- this contains the impementation of 5 stage superscalar piepline in verilog
DifferentialManchestercodedecodingverilogcode
- 差分曼彻斯特码解码的verilog代码 -Differential Manchester code decoding verilog code
debounce
- 按键消抖程序，用Verilog硬件描述语言编写，实现了按键消抖动作-Buffeting eliminate key procedures, using Verilog hardware descr iption language, the realization of the keys for jitter elimination
timeclock
- 数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。-Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on.
Johnson-counter-with-verilog-design
- the file contains verilog code for johnson counter
Mod13-counter-with-verilog-design
- verilog code for mod13 counter source code-verilog code for mod13 counter source code
ringcounter-with-verilog-design
- Ring counter souce code in verilog
Serial-parallel-multiplier-verilog-design
- Serial parallel multiplier verilog design source code