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带自适应波特率发生器UART实现，经过FPGA验证的！,UART baud rate generator with adaptive realization, after FPGA validation!
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软件UART程序，用PCA做波特率发生器，使用的是C8051F000单片机-Software UART procedure, PCA to do with the baud rate generator, using a single-chip C8051F000
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串口设置：包括初始化及应用；串口调试方面直接能用上-// This sample uses the UART to communicate with a PC. Therefore it sets up the internal
// Baud Rate Generator (BRG). The LPC900 receives a command ( S ), sent by the PC and
// sends out a response, which can be display
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RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
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本应用笔记讨论基于C8051Fxxx系列器件的软件UART实现方法本文给出两个完整的例子一个用PCA为波特率发生器的C语言程序和一个用定时器0为波特率发生器的汇编语言程序-Application Notes discuss the C8051Fxxx series of devices based on the software UART implementation integrity of this paper two examples of a baud rate generator wi
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URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simu
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波特率发生器的VHDL源码。适用于uart、spi、IIC-Baud rate generator VHDL source code. Apply to uart, spi, IIC
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开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
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一个串口程序，用定时器作为波特率发生器，只要知道波特率便可以直接初使化uart，具有很强的适应能力的程序-A serial program, with the timer as a baud rate generator, as long as they can directly know the baud rate initialization uart, has a strong ability to adapt procedures
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UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA器件设计与实现UART。
-UART is a widely used serial data communication circuits. This design includes UART transmitter, receiver and baud rate generator. Design and Application of EDA technology, ba
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基于UART的VHDL程序，包括顶层程序、波特率发生器程序、UART发送器程序、UART接收器程序4部分程序。有详细注释，并在每个程序后附上一张仿真波形图，便于理解和验证。-UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four par
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ADUC841串口通讯，c语言编写，用t3作为波特率发生器，电路外接晶振频率为11.0592MHZ.另外注意PLLCON寄存器可能需要在头文件中定义。-ADUC841 serial communication, c language, with t3 as the baud rate generator, an external crystal frequency Circuit 11.0592MHZ. Also note that PLLCON registers may need to de
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LYS-51开发板串口通信驱动，包括初始化，写字节，写字串函数。在12m晶振下，使用Timer2作为波特率发生器。-LYS-51 development board serial communication drivers, including the initialization, write byte, write string function. In the 12m crystal, the use Timer2 as a baud rate generator.
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带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequ
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串口通信控制器的Verilog实现。包含4个模块：顶层模块、波特率发生器模块、发送模块和接收模块-The serial communication controller Verilog. Contains four modules: the top-level module, the baud rate generator module, transmitting module and receiver module
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lcd
显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
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430 UART程序实例 包括初始化代码设置，中断方法实现-Descr iption: This program demonstrates a half-duplex 2400-baud UART using
Timer_A3 and a 32kHz crystal. The program will wait in LPM3, echoing
back a received character using 8N1 protocal. The 32768 cryst
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URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
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本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块，分为发送模块，接受模块和波特率产生模块。-This routine is verilog hardware descr iption language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generato
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verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
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