资源列表
tpc_vhd.rar
- 完整的TPC编译码VHDL程序，直接就可以运行,TPC encoder and decoder
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
hdlc
- HDLC接口协议的FPGA实现使用verilog-design of HDLC
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
RS-422standardmodulev2
- rs422标准通讯模块 异步收发 verilog语言编写-rs422 standard communication module asynchronous receiver verilog language
AT510-BU-98000-r0p0-00rel0
- CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！-CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable
endat
- endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值-endat 2.2 interface cores, sending commands to the encoder or received the encoder position values
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
addersub4
- 用拨码开关输入两个四位二进制数，按下运算按钮后，以 led 的方式显示运算的结果。拓展 1 ．在基本功能实现前提下，增加一个清零功能。 2 ．更换显示方式，结果用数码管进行显示。 3 ．对溢出值的考虑。如果发生溢出现象，则数码管显示“ E ”。 -Use DIP switches to enter two four binary numbers, press the operation button to display the results led the operation
tlk2711test
- 用verilog语言实现了tlk2711serdes芯片的高速串行功能，包含工程与仿真文件，亲测可用-Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available