资源列表
FPGA
- fpga 设计经典指导原则，非常经典，对于深入理解FPGA设计方法有很好的帮助-FPGA design of the guiding principles of the classic, very classic, for better understanding of FPGA design methods have a very good help
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
T3_USB_OUT
- cy7c68013向外部发送一个数据 ，发送至fpga，fpga的实例程序 -CY7C68013 to send an external data, sent to the fpga, fpga examples of procedures
median
- 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
kuoping
- fpga嵌入式设计 扩频接收机设计 有matlab 和vhdl 对比情况-Design of spread-spectrum receiver embedded FPGA design and VHDL contrast matlab
1
- 基于eda中vhdl语言的一位全加器的设计，详细的设计过程和实验现象，相互学习-Based on EDA VHDL language in a full adder design, detailed design process and the experimental phenomena and learn from each other
VHDL_digital
- 《数字系统设计与VerilogHDL》 阐述数字系统设计方法，重点对用vhdl设计开发常用的数字电路和数字系统进行具体阐述，配合大量设计实例。-err
ARM7_verilog
- arm 7 verilog code used setup soc
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
UART
- 基于FPGA的UART实现 用VHDL编程-The UART-based FPGA using VHDL Programming