资源列表
ssz
- 数字钟,用VHDL写的各个模块,顶层用图形编辑,在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
project_UHF_ddc
- vhdl语言写的数字下变频的实现,整个工程文件,xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
add
- Verilog hdl语言 常用加法器设计,可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
divide
- Verilog hdl语言的常用除法器设计,可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
VHDLplj
- (1)设计4位十进制频率计测量范围: 1Hz~9999Hz (2)测量的数值通过4个数码管显示 (3)频率超过9999Hz时,溢出指示灯亮,可以作为扩大测量范围的接口-(1) the design of four decimal frequency measuring range: 1Hz ~ 9999Hz (2) measurement values through four digital tube display (3) the frequency of more than 999
PWM
- 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
CPLD_Config
- 用Altera CPLD做为控制器从Flash上读取image文件对Altera FPGA编程-Altera CPLD used as a controller to read image from the Flash on the Altera FPGA programming
2DPSK
- 用vhdl语言实现2DPSK数字传输-VHDL language used to achieve digital transmission 2DPSK
edawblzkq
- eda微波炉程序控制器 初学vhdl语言的控制程序设计-microwave EDA VHDL language learning program controller of the control procedures designed
ff
- QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。-QUARTUS II platform based on the VHDL language elevator system control procedures.
SD_Host_Model_513_02
- 可做SD的simulation model-SD can do the simulation model
diaziqin
- 这是一个简单的VHDL电子琴程序,分为三个源代码,与其他的源代码不同的是,这个代码比较简单,适合于初学者。-This is a simple flower VHDL procedures, divided into three source code, source code with other difference is that this code is relatively simple, suitable for beginners.