资源列表
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
dianti
- 用verilog写的电梯控制器内附测试文件和实验报告 -Use verilog to write elevator controller with the test documentation and test reports
v5_config
- xilinx v5的在线，上位机配置程序-xilinx v5 configuration
CPUVHDL
- CPU+VHDL代码及详细注释\一个老外写的 200多行代码-CPU+ VHDL code and detailed notes \ a foreigner wrote more than 200 lines of code
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
Testbenching-Example
- FPGA设计测试用例介绍PPT文档，对于初写测试用例很有帮助。-FPGA Design of test cases to introduce PPT files, helpful for the beginning of writing test cases.
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
FPGA_SPI_Trans
- FPGA模拟SPI与MSP430通讯Verilog程序-A verilog program of fpga talks to mcu msp430 using spi
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
202206
- 十字路*通灯的设计，基于EDA VHDL语言编写，内容比较全面-Traffic lights at the crossroads of design, EDA VHDL-based languages, as a more comprehensive