资源列表
SD_Host_Model_513_02
- 可做SD的simulation model-SD can do the simulation model
diaziqin
- 这是一个简单的VHDL电子琴程序，分为三个源代码，与其他的源代码不同的是，这个代码比较简单，适合于初学者。-This is a simple flower VHDL procedures, divided into three source code, source code with other difference is that this code is relatively simple, suitable for beginners.
disanci
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
AM
- FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Lift
- VHDL编写的6层电梯控制器，可在Altera的CPLD系统运行实验，内附实验报告-VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
erwertwerwe
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
ref-ddr-sdram-vhdl
- 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
ref-sdr-sdram-vhdl
- 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
RS_204_188_decoder
- 使用verilog完成了RS编码的设计，编码参数为输入188，输出204-The use of Verilog coding RS completed the design, coding parameters for the importation of 188, the output 204
elecfans.com-74783742
- FPGA的重要实例,如PSK调制和解调,ASK,FSK-An important example of FPGA, such as PSK modulation and demodulation, ASK, FSK
fpgacrosslightcontroller
- fpga交通控制灯，利用quartus 实现，-FPGA traffic control lights, the use of Quartus achieved
run_watch
- 提供一个数字秒表的EDA设计实例，内故有VHDL源代码，并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.