资源列表
booth_mult
- ＦＰＧＡ的ｖｒｉｌｏｇ ＨＤＬ代码，布尔乘法器-FPGA-vrilog HDL code, the Boolean multiplier
kuopin_vhdl
- 直接序列扩频的VHDL实现，论文里面提供了较好的源码和方案设计-Direct Sequence Spread Spectrum of the VHDL implementation, research papers which provide a better source and program design
ElevatorcontrollerandsimulationwithVHDL
- 电梯控制器VHDL程序与仿真 功能：6层楼的电梯控制系统。包括原理图及仿真结果。-Elevator controller and simulation of VHDL program features: six-story elevator control system. Including schematics and simulation results.
mjpeg-decoder_latest.tar
- 基于fpga实现的硬件jpeg格式图片的解码器-jpeg decoder based on FPGA
sdram
- SDRAM驱动器，自己项目利用的，已经经过实际验证-sdram controller
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA
- Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
Xilinx-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Advanced_Digital_Design_with_the_Verilog
- Verilog 语言的高级数字系统设计，原版书籍，很全面-Verilog language, advanced digital system design, original books, very comprehensive
sdram_controler
- SDRAM 读写控制器的 verilog 三星公司源代码-verilog design for SDRAM read and write
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
altera_up_avalon_irda
- Altera大学计划的红外通讯IP，avalon接口-Altera University Program of the infrared communication IP, avalon interface
32bitBoothmultiplier
- 32位布思乘法器VHDL实现，2个32位数相乘-32-bit Booth multiplier VHDL implementation, two 32-digit multiplication