资源列表
DSP_FIR_Lab
- DSP的FIR实验，包含三种FIR实现形式，直接型，转置型，累加型，并且附带testbench,经过modesim测试没问题。-This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
lcdok
- 自己写的LCD控制器，在EP1C3T140C8上跑过，对初学者有帮助，实在的VHDL代码-Write your own LCD controller, in the EP1C3T140C8 last ran for help for beginners, it' s VHDL code
chufaqi
- VHDL除法器设计，配合移位减法方式设计除法器以节省硬件成本-VHDL divider design
dianti
- FPGA的电梯控制程序，用vhdl语言实现电梯的控制的代码-FPGA elevator control program, using vhdl language implementation code for the control of the elevator
chengfa-verilog
- booth乘法器verilog代码.利用移位和加法来实现乘法-verilog
OCMJ_LCD
- 超大液晶显示程序-金鹏0CMJ15X20D系列。MSP430上验证通过。-Large liquid crystal display programs- Jinpeng 0CMJ15X20D series. Verified by the MSP430.
xb
- 用汉宁窗设计一个FIR高通数字滤波器，满足以下参数要求：通带边界频率ωp=0.7π，通带内衰减函数αp=0.4dB；阻带边界频率Ωs=0.4π，阻带内衰减函数为αs=55dB。-With the Hanning window design an FIR high-pass digital filter to meet the requirements the following parameters: passband edge frequency ωp = 0.7π, pass-band at
HDLC_E1
- E1到HDLC转换 实现E1到以太网 E1到HDLC转换 实现E1到以太网-E1 TO HDLC E1 TO ETHETH
qiangda
- EDA课程设计，是四路智力抢答器的vdhl程序，里面还有我自己录课程视频。仅作为参考！-EDA curriculum design, is a quad of vdhl intellectual Responder program, which was recorded courses and my own video. Only as a reference!
cunchushiboqi
- 用vhdl编写数字存储示波器，通过调试，仿真环境是maxplus-Vhdl digital storage oscilloscope with the preparation, through debugging, simulation environment is maxplusII
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input
add_tree_mult
- ＦＰＧＡ的ｖｒｉｌｏｇ ＨＤＬ代码，树型乘法器-FPGA-vrilog HDL code, tree multiplier